Taiwan Semiconductor Manufacturing Company Limited (TSMC) has announced plans to increase production of Tesla’s next-generation Dojo training tile, signaling a significant step forward in the development of advanced semiconductor technology. The company also revealed its intentions to offer more powerful tiles in the future.
During the TSMC North American Technology Symposium, the company outlined its roadmaps for semiconductor and chip packaging technologies. According to a report from IEEE Spectrum, TSMC confirmed that Tesla’s next-generation Dojo training tile is already in production. This follows Tesla’s order in 2023 for D1 chips of its own design from TSMC.
TSMC is aiming to offer technology for more complex wafer-scale systems by 2027, which will provide 40 times more computing power than current systems. This advancement will be achieved through advanced packaging technology, allowing a single processor to be made from more silicon.
The D1 chip, which is the main component of the Tesla Dojo supercomputer, is a “system-on-wafer” that occupies an entire 300 mm silicon wafer and contains 25 accelerators and other functional elements. TSMC produces the D1 using 7nm technology. Tesla initially ordered about 5,000 of these chips from TSMC in 2023, with plans to double the number to 10,000 chips in 2024 and further increase purchases in 2025. Tesla aims to achieve a performance level of 100 exaflops for its Dojo supercomputer by the end of 2024, indicating ongoing scaling efforts for the system.
Dojo is expected to be capable of performing an exaflop, or 1 quintillion floating-point operations, per second. This level of computational power is groundbreaking, as it can complete tasks in seconds that would take a regular desktop computer billions of years to accomplish.
